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I am a Multimedia Machine Learning System Architect at Google. I received the BS degree in EECS and the PhD degree in EE from National Tsing Hua University, Taiwan. My research interests include algorithm-hardware co-optimization and energy-efficient VLSI architecture design for image processing, computer vision, and deep learning applications. I have a strong publication record as the first author of papers in top-tier conferences, such as ISSCC and ESSCIRC, and leading journals, including JSSC and IEEE Access. Additionally, I have co-authored several publications in other prestigious venues like MICRO, ISICAS, TCAS-I, and SSC-L. I have hands-on experience in developing real-time chip and FPGA SoC demonstration platforms and have led digital VLSI circuit tape-out projects using cell-based design flow in 40nm and 16nm. |
Email: ycding@gapp.nthu.edu.tw ycting0423@gmail.com |
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(published as: Yu-Chun Ding) |
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Yu-Chun Ding, Chia-Yu Chang, Hui-Yun Tsai, Chun-Yeh Lin, Hao-Jiun Tu, Yu-Ching Su, Kai-Feng Chang, Tsung-Han Hsieh, Wen-Ching Chen, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, and Chao-Tsung Huang IEEE Journal of Solid-State Circuits (JSSC), 2026 Video record of the FPGA-aided chip demonstration system |
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Yu-Chun Ding, Chia-Yu Chang, Chun-Yeh Lin, Hui-Yun Tsai, Hao-Jiun Tu, Kai-Feng Chang, Yu-Ching Su, Tsung-Han Hsieh, Yu-Kuan Jian, Wen-Ching Chen, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, and Chao-Tsung Huang IEEE International Solid-State Circuits Conference (ISSCC), 2025 Video record of the FPGA-aided chip demonstration system (Invited to attend the Demonstration Session in ISSCC 2025) |
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Yu-Chun Ding, Chia-Yu Chang, Pei-Rong Li, Chao-Tsung Huang, Yung-Chen Lin, Tsung Chen, Wei-Lun Lin, Cheng-Ting Lee, Fan-Yi Lin, and Yuan-Hao Huang IEEE Access, 2025 |
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Kai-Pin Lin, Yu-Chun Ding, Chun-Yeh Lin, Yong-Tai Chen, and Chao-Tsung Huang IEEE Solid-State Circuits Letters (SSC-L), 2024 Video record of the FPGA-aided chip demonstration system |
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Yu-Chun Ding, Kai-Pin Lin, Chi-Wen Weng, Li-Wei Wang, Huan-Ching Wang, Chun-Yeh Lin, Yong-Tai Chen, and Chao-Tsung Huang IEEE European Solid-State Circuits Conference (ESSCIRC), 2022 Video record of the FPGA-aided chip demonstration system |
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Ching-Te Chiu, Yu-Chun Ding, Wei-Chen Lin, Wei-Jyun Chen, Shu-Yun Wu, Chao-Tsung Huang, Chun-Yeh Lin, Chia-Yu Chang, Meng-Jui Lee, Shimazu Tatsunori, Tsung Chen, Fan-Yi Lin, and Yuan-Hao Huang IEEE Transactions on Circuits and Systems—I: Regular Papers (TCAS-I), 2022 IEEE International Symposium on Integrated Circuits and Systems (ISICAS), 2022 Pre-recorded video for the presentation in ISICAS 2022 |
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Ching-Chen Wang, Yu-Chun Ding, Ching-Te Chiu, Chao-Tsung Huang, Yen-Yu Cheng, Shih-Yi Sun, Chih-Han Cheng, and Hsueh-Kai Kuo IEEE Transactions on Circuits and Systems—I: Regular Papers (TCAS-I), 2021 Pre-recorded video for the invited presentation in the 2022 VLSI Design/CAD Symposium |
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Yu-Chun Ding IEEE International Solid-State Circuits Conference Student Research Preview (ISSCC SRP), 2021 |
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Ching-Chen Wang, Ching-Te Chiu, Chao-Tsung Huang, Yu-Chun Ding, and Li-Wei Wang IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2020 |
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Chao-Tsung Huang, Yu-Chun Ding, Huan Ching Wang, Chi-Wen Weng, Kai-Pin Lin, Li-Wei Wang, and Li-De Chen IEEE/ACM International Symposium on Microarchitecture (MICRO), 2019 |
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Last Update: Jun. 2026
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